During semiconductor wafer processing, integrated circuits or die are formed on thin wafer substrates that are made of silicon or other materials. After wafer processing is complete, the die must be singulated or separated into individual die before they are packaged. This singulation process is referred to as wafer dicing. One technique that is used for wafer dicing is mechanical sawing. With this approach, a high speed rotating saw is used to separate adjacent die along kerf lines, which are also known as dicing channels or streets. Another technique that is used for wafer dicing is a laser-based approach that is referred to as stealth dicing. Due to the abrasive nature of performing mechanical dicing with a saw, chipping, mechanical stress and crack formation can occur near the outer edges of the wafer which can reduce die reliability and wafer yields. Because of the intense thermal effect that laser dicing has on a silicon wafer, laser dicing can also cause crack formation and deposits near the outer edges of the wafer which can reduce die reliability and wafer yields.
Plasma dicing is another technique that is used for wafer dicing. Because plasma dicing is a dry etch process that does not require physical or thermal contact with a wafer, many of the problems inherent with mechanical or laser dicing can be avoided. Plasma dicing is based on a multiplexed deep reactive ion etching (DRIE) technique and can be performed on wafers mounted in standard tape frames or carriers. To prepare wafers for plasma dicing, a lithographic process is used to define the kerf lines that will be etched on the wafer. The kerf lines typically extend to the edge of the wafer and therefore can include adjacent partial die near the wafer edges. This lithographic process enables direct access by plasma during the etching step to etch through the wafer along the kerf lines. With plasma dicing after grinding (PDAG), also referred to as dicing post grinding (DPG), the wafer is thinned and mounted onto an adhesive underlayer or glue within a wafer carrier before undergoing the plasma singulation process.
If relatively large die are to be plasma diced on a wafer, the lithographic process performed prior to dicing will expose kerf lines that extend up to the edge of the wafer. Due to their size and corresponding large contact area with the adhesive underlayer in the wafer carrier, these die, including the partial die located near the edge of the wafer, remain temporarily well-bonded to the adhesive underlayer after plasma singulation and during subsequent processing steps (e.g., lamination, demounting, etc. . . . ), before pick and place tape release techniques are used to remove the die from the adhesive underlayer for packaging.
Smaller die will have a smaller contact area with the adhesive underlayer. Because the lithographic process performed prior to plasma dicing will expose kerf lines that extend up to the edge of the wafer, these die, and especially the partial die located near the edge of the wafer, are significantly more prone to chipping and cracking and subsequent delamination from the adhesive underlayer after plasma singulation is complete.
While plasma dicing can reduce the overall amount of wafer chipping and cracking as compared to other dicing approaches such as laser dicing, all dicing methods will have the chipping, cracking and deposit formation problems inherent with smaller die. This can be a significant problem for integrated circuit manufacturers that supply integrated circuits to customers in the automotive and industrial applications areas that impose zero defect requirement standards on their suppliers. One technique that has been used to help avoid the chipping and cracking problem with smaller die is to shield or prevent kerf lines near the outer edge of the wafer from being etched. Use of this technique however will leave an unetched ring of material around the edge of the wafer that requires an additional process step for removal before pick and place techniques can be used for packaging the die.